Typically, a transistor used to amplify a time-varying (AC) signal is biased at a predetermined quiescent (DC) operating point about which the amplified AC signal transitions.
FIG. 1 is a diagram of an amplifier stage 10 for an electronic system, such as a cell phone or wireless modem.
The amplifier stage 10 includes a biased amplifier transistor 12 for amplifying a radio-frequency (RF) signal for transmission to a remote receiver (not shown). The amplifier stage 10 also includes a circuit 14 for biasing the transistor 12, a generator 16 for generating the RF signal from an input signal, RF chokes 18 and 20, a DC blocking capacitor 22, and a load 24 across which the transistor generates the amplified RF signal Vo. If the amplifier stage 10 is an intermediate amplifier stage, then the input signal is a data signal or an intermediate RF signal from a previous amplifier stage, and the load 24 is a subsequent amplifier stage; alternatively, if the amplifier stage 10 is the final amplifier stage, then the load is an antenna.
The amplifier transistor 12 is a type III-IV (e.g., GaAs) field-effect transistor having a control node (here a gate G), a first conduction node (here a drain D), and a second conduction node (here a source S).
The bias circuit 14 generates a DC bias voltage Vbias across the gate G and source S nodes of the transistor 12, and Vbias causes the drain D of the transistor to sink a quiescent bias current Ibias; therefore, the RF current that the transistor draws to generate Vo transitions about Ibias.
The choke 18 isolates the bias circuit 14 from the RF signal, the choke 20 isolates the supply Vtransmit from Vo, and the capacitor 22 isolates the generator 16 from Vbias.
In operation, the transistor 12 amplifies the RF signal from the generator 16 by generating at the drain D an RF current that “rides” on Ibias. This RF current generates Vo, which “rides” on the DC bias voltage established by Ibias 
FIG. 2 is a diagram of the bias circuit 14 of FIG. 1. Together, the transistor 12 and the circuit 14 form a conventional buffered Widlar current mirror.
The bias circuit 14 includes a current source 30 (here a reference resistor as discussed in the proceeding paragraph), a reference node 32, a reference stage 34, a buffer stage 36, and a bias node 38.
The current source 30 includes a resistor 40, which sources a reference current Iref to the reference node 32. Iref is proportional to the supply voltage Vref and inversely proportional to the value of the resistor 40.
Alternately, the current source 30 may include a diode-connected or fixed-bias transistor (neither shown in FIG. 2).
The reference stage 34 includes a reference field-effect GaAs transistor 42, which is matched to the amplifier transistor 12 of FIG. 1, and includes a resistor 44. Typically, the transistors 12 and 42 are disposed on the same integrated circuit (IC) die, which results in the transistors being closely matched.
The buffer stage 36 includes a buffer field-effect GaAs transistor 46, which is matched to the transistors 12 and 42 and which has approximately the same channel dimensions as the reference transistor 42.
The buffer transistor 46 is configured as a source follower between the reference node 32 and the bias node 38, and the buffer supply voltage Vbuffer may be the same as or different than Vref.
Operation of the amplifier stage 10 is now discussed where the stage has the transistor parameters, resistor values, and supply-voltage values as respectively shown in Tables I-III.
TABLE IReferenceBufferAmplifierTransistor 42Transistor 46Transistor 12Channel100 μm100 μm960 μmWidth(assuming alltransistorshave thesame channellength)
TABLE IIResistor 40Resistor 44Resistance7.12 KΩ1.39 KΩ
TABLE IIIVrefVbufferVoltage1.0 V3.6 V
The reference transistor 42 sinks the current Iref, and generates across its gate (G)-to-source (S) junction, and thus across the resistor 44, the bias voltage Vbias, which is proportional to Iref. Because the reference transistor 42 and the amplifier transistor 12 (FIG. 1) are matched and have the same gate-to-source voltage Vbias, then ideally:Ibias=spredicted·Iref  (1)where Spredicted is a scale factor that depends on the channel dimensions of the transistors 12 and 42—Spredicted may depend on other quantities such as the output conductances of transistors 12 and 42, but these dependencies are ignored for purposes of this analysis. For example, per Table I, where the transistors 12 and 42 have the same channel length L, the transistor 42 has a channel width W42=100, and the transistor 12 has a channel width W12=960, then ideally:Spredicted=W12/W42=960/100=9.6  (2)Therefore, from equations (1) and (2), one would anticipate Ibias=9.6·Iref.
Unfortunately, as discussed below, the amplifier stage 10 may experience one or more problems related to the biasing of the amplifier transistor 12.
FIG. 3 is a plot of the supply voltage Vtransmission of FIG. 1 versus time, where, as further discussed below, Vtransmission transitions from a voltage level Vhigh=3.6 V to a voltage level Vlow=1.0 V at a time t.
FIG. 4 is a plot of the bias current Ibias of FIG. 1 versus time, where, as further discussed below, Ibias experiences an undesirable transient commencing when Vtransmission transitions from Vhigh to Vlow.
Referring to FIGS. 1-3, a system that includes the amplifier stage 10 may switch Vtransmission between two voltage levels Vhigh and Vlow depending on the transmitting-power requirements. For example, if a remote receiver (not shown) is relatively close to the system, then the system may reduce the power at which it transmits the RF signal by switching Vtransmission to Vlow If the system is battery powered, then switching Vtransmission to Vlow when a low transmission power is sufficient may prolong the battery life. Conversely, if the remote receiver is relatively far away from the system, then the system may increase the power at which it transmits the RF signal by switching Vtransmission to Vhigh.
But referring to FIG. 4, switching Vtransmission from Vhigh to Vlow causes Ibias to experience a transient response that significantly overshoots its settled value, for example by 45% or more, and that has a significant duration (e.g., ˜100 microseconds).
It has been theorized that a cause for this spiking of Ibias may be charge traps that are present in the GaAs amplifier transistor 12 (FIG. 1) and that temporarily alter the threshold voltage of the amplifier transistor in response to the switching of Vtransmission. When Vtransmission switches, the voltage at the drain node D of the amplifier transistor 12 changes. But the cumulative voltage across the charge traps, which act like capacitors, does not change instantaneously. Therefore, this charge-trap voltage temporarily alters the threshold voltage of the amplifier transistor 12, thus causing a change in Ibias even though Vbias is unchanged.
As the charge traps rebalance their charge, Ibias increases back toward its previous level, but settles at a new, lower level because Ibias has a dependence on the voltage at the drain D of the transistor 12.
Although not shown in FIG. 4, switching Vtransmission from Vlow to Vhigh causes Ibias to experience a transient response having a positive overshoot and duration similar (but having opposite polarity in the case of the overshoot) to those of the negative transient.
Unfortunately, the overshoot, duration, or both the overshoot and duration of such a transient in Ibias may render the amplifier stage 10 unsuitable for some applications. For example, the system incorporating the stage 10 may need to halt transmission of the RF signal for the duration of the transient, and this may limit the data-transmission rate to below a desired rate.
Still referring to FIGS. 1-4, a related problem is that due to the transistor output conductance, the difference between the quiescent (i.e., settled) values for Ibias at Vtransmission=Vhigh and Vtransmission=Vlow may be too large for some applications for which one might otherwise use the amplifier stage 10.
FIG. 5 is a plot of the actual scale factor sactual(=Ibias/Iref) versus the magnitude of Iref for the above-described implementation of the amplifier stage 10 of FIG. 1.
Referring to FIGS. 1, 2, and 5, another problem with the stage 10 is that the actual scale factor sactual between Ibias and Iref may differ significantly from the value of spredicted calculated from equation (2), and this difference may cause the actual value of Ibias to differ significantly from the design value of Ibias.
For example, where spredicted=(W12)/(W42)=9.6 per equation (2), one would expect Ibias≈10·Iref (scale factor sactual≈10) from equation (1).
But referring to FIG. 5, a computer simulation shows that for 0.1 milliampere (mA)≦Iref≦4.5 mA, 18≧sactual≧16, which is an increase of 60% -80% from the value of spredicted≈10 given by equation (2). This increase results in the actual value of Ibias being approximately 1.5-2 times greater than the value predicted by equations (1) and (2).
It has been theorized that one cause of this discrepancy between the value of spredicted given by equation (2) and the value of sactual is the relatively low voltage (e.g., less than 1.0 V) at the drain D of the reference transistor 42. At this relatively low drain voltage, the transistor 42 operates closer to its resistive, or triode, region. When the transistor 42 operates in its triode region, Iref is much more dependent on the drain voltage than it is when the transistor operates in its saturation region. Therefore, for equation (2) to yield an accurate value for spredicted while the transistor 42 is operating in its triode region, the DC voltage at the drain D of the transistor 12 must substantially equal the DC voltage at the drain D of the transistor 42. But because during operation of the amplifier stage 10 the voltage at the drain of the transistor 12 is typically higher than the voltage at the drain of the transistor 42, equation (2) may yield a relatively inaccurate value for spredicted.